1. Field of the Invention
The present invention concerns a semiconductor optical device in the field of optical communication and the like, as well as a manufacturing method thereof.
2. Related Background Art
In recent years, increase for the transmission speed of optical communication has bee progressed. In order to attain a semiconductor optical device at a transmission speed exceeding 10 Gbit/s, it is important to decrease the parasitic capacitance pertaining to the semiconductor optical device.
Description is to be made to an existent structure of a semiconductor optical device and a manufacturing method thereof. A semiconductor laser at a transmission speed 10 Gbit/s has, as shown in FIG. 10, a semiconductor mesa formed on an InP substrate 101, in which both sides of the semiconductor mesa are buried with an Fe-InP semiconductor 102 for planarization. Since the growth in burying is conducted usually at a high temperature of about 600° C., thermal diffusion 103 of a dopant (for example, Zn) from the semiconductor mesa portion to the Fe-InP layer 102 occurs. Further, a pad electrode 104 is formed on the Fe-InP semiconductor 102 with a dielectric constant of 12.6. Therefore, the parasitic capacitance is formed of PIN junction capacitance 105, diffusion capacitance 106 on both sides of the cross sectional shape inverted mesa (inverted trapezoidal) and a pad capacitance 107.
In order to decrease the parasitic capacitance pertaining to the semiconductor optical device, it has been proposed a ridge structure in which both sides of the inverted mesa cross sectional structure are buried with a polyimide resin 201 with a dielectric constant of 3.6. Since the structure is free of the thermal diffusion 103 of the dopant and the pad electrode 104 is formed on the polyimide 201 of low dielectric constant, the parasitic capacitance can be decreased greatly.
The polyimide resin on both sides of the mesa cross sectional structure is planarized by an etching back method using a dry etching apparatus. The etching back method is one of dry etching methods, which is a technique of planarizing the unevenness on the surface of a semiconductor substrate only due to the directionality of dry etching without using a mask material such as a resist.
FIG. 12 shows a flow of manufacturing an InP series ridge waveguide channel type semiconductor laser in which the both sides of the ridge are buried with a polyimide resin 201. FIG. 13 shows an existent dry etching apparatus used for manufacturing the flow shown in FIG. 12.
At first, after forming a multi-layered structure comprising an active layer 401, an InP clad layer 402 and a contact layer 403 on an InP substrate 101 for forming an optical waveguide channel, the contact layer 403 is fabricated into a stripe structure with a stripe width of 2.0 μm and a trench width of 10 μm on both sides of the stripe by using a CVD oxide film of 100 nm (hereinafter referred to as an SiO2 film) 404 (FIG. 12(A)). Successively, the InP clad layer 402 is etched by using wet etching with a liquid mixture of hydrochloric acid and phosphoric acid to form a ridge waveguide channel of an inverted mesa cross sectional shape as shown in FIG. 12(B). Then, a passivation film 405 of 0.5 μm thickness is formed over the entire substrate by a CVD method. Then, a polyimide resin 201 is coated over the entire substrate (FIG. 12(C)).
Then, a dry etching apparatus shown in FIG. 13 is used and the polyimide resin 201 in the trenches on both sides of the ridge is planarized and, at the same time, the polyimide resin 201 in the portions other than the trenches on both sides of the ridge waveguide channel is completely removed by an etching back method using an oxygen-argon gas mixture with addition of a fluoric gas (FIG. 12(D)).
The dry etching apparatus shown in FIG. 13 has a reaction chamber 501 installed therein, which has a lower electrode 504 that also serves as a holder for a tray 503 for transportation of a semiconductor substrate 502 or a wafer and an upper electrode 505 opposed to the lower electrode 504. The lower electrode 504 and the upper electrode 505 are used as electrodes for applying power that apply an RF power or DC power to a reaction gas introduced between both of the electrodes to convert the gas into plasmas. In the illustrated embodiment, an RF supply source 507 is connected to the lower electrode 504 by way of a matching box 506. An exhaustion device 509 connected with an exhaustion pump by way of an on-off valve 508 is laid in the reaction chamber 501, and a pipeline of a gas supply portion is connected. The gas supply portion contains an oxygen reservoir 512, an argon reservoir 213 and a fluoric gas reservoir 514 for supplying a required amount of reaction gas by way of gas flow meters 510 and on-off valves 511. Further, the gas reservoirs are installed in a cylinder cabinet for safety. Further, the reaction chamber 501 is provided with a preparatory chamber 515 for transportation of wafers which can transport wafers without exposing the reaction chamber 501 to atmospheric air.
Then, the passivation film 405 in the current injection region ridge waveguide channel is removed. In this case, if needle-like reaction products 406 remain over the contact layer, they cause uneven etching to increase the device resistance. Then, an upper electrode 407 of about 1 μm thickness comprising Ti/Pt/Au is formed by an EB vapor deposition method. Then, after pattering the upper electrode 407 by ion milling, it is passed through steps such as rear face polishing, formation of the lower electrode 408 and electrode alloying (FIG. 12(E)). After passing the steps described above, the wafer is cleaved in a bar shape with a 200 μm cavity and, after forming a reflection protective film on the cleaved surface, it is separated into devices each in chip-like shape.
On the other hand, Japanese Laid-Open Patent No. H 3(1991)-177020 discloses to form a cover material that shields the electrode for mounting a work from energy rays in an etching apparatus with a fluorine-containing resin such as teflon (registered trademark) thereby increasing the etching rate speed of SiO2 series films.